Memory Systems for the Heterogeneous Era

Si è svolta a luglio la 15esima edizione della International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2019), organizzata da HiPEAC in collaborazione con TETRAMAX Innovation Action e Eurolab4HPC . Come per le edizioni precedenti, Reiss Romoli ha avuto un ruolo chiave nella organizzazione e gestione dell’evento.

Durante la Summer School i partecipanti seguono 4 corsi, scelti tra i 12 del programma, oltre a un Keynote Speach e a un Invited Talk.

A questa edizione hanno partecipato circa 220 ricercatori provenienti da molte delle università europee ed esperti del settore, con docenti provenienti da rinomate università americane e da industrie di punta del settore.

Il dott. Aamer Jamel, che è Principal Research Scientist nell’ Architecture Research Group (ARG) di NVIDIA, ha contribuito alla Summer School con un corso su:

Memory Systems for the Heterogeneous Era

Emerging high performance computing systems consist of multiple latency optimized processors (e.g., CPUs) and throughput optimized processors (e.g. GPUs) interconnected using a high performance network.

The performance of such heterogeneous systems is directly dependent on the processor memory hierarchy. This course covers the trade-offs when designing a high performing memory hierarchy for CPUs, GPUs, and heterogeneous systems consisting of multiple CPUs and GPUs.

It has been shown that different design constraints yield different solutions when designing the memory hierarchy. The lectures cover fundamental design concepts and state-of-the-art research in virtual memory, cache hierarchy, and main memory systems.
The course also includes personal experiences on commercializing research ideas and also include discussions topics on areas for continued research.

Aamer Jaleel, NVIDIA

Aamer Jaleel is a Principal Research Scientist in the Architecture Research Group (ARG) at NVIDIA. Prior to joining NVIDIA, Dr. Jaleel was a Principal Engineer in the Versatile Systems and Simulation Advanced Development (VSSAD) group in Intel. During his decade-long career at Intel, Dr. Jaleel's research work contributed towards enhancement in performance modelling and cache hierarchy improvements of Intel’s next generation microprocessors. Dr. Jaleel received his Ph.D. in Electrical Engineering from the University of Maryland, College Park in 2006. He received his B.S. and M.S. in Computer Engineering, also from the University of Maryland, College Park in 2000 and 2002 respectively. Dr. Jaleel has co-authored more than a dozen patents and over 30 technical publications.